memory data bus
英 [ˈmeməri ˈdeɪtə bʌs]
美 [ˈmeməri ˈdeɪtə bʌs]
网络 存储数据总线
双语例句
- The read pointer is connected to the memory bank for addressing a second memory location to read a datum stored therein onto an output data bus.
所述读取指针连接到存储体，用于寻址第二存储器位置，以将存储在其中的数据读取到输出数据总线上。 - Based on the designed PCI bus memory card, the signal definitions and command operations of PCI bus and the process of data access on the PCI bus are discussed in detail.
以自行开发的PCI总线存储卡为背景，详细论述了PCI总线的信号定义和命令操作，以及总线上的数据传输过程。 - The memory system of dual channel A/ D automatic acquisition is studied in this paper. Using transceivers and gating controllers, the data bus and address bus of RAM are respectively controlled.
本文研究了双通道A/D自动采集存储系统，利用数据收发器及数据选通控制器分别控制RAM的数据线及地址控制线。 - This article researches expansive technology about large capacity memory in monolithic computer system, The paper attaches importance to no conflict on address design and separation of data bus between basic and expansive memory.
对单片机应用系统中大容量存储器的扩展技术进行了深入的研究，着重论述了存储地址的无冲突设计和基本/扩展存储器间数据线的隔离问题。 - The memory structure, constitution of data communication channel and system bus are analyzed, and the algorithm allocating, algorithm mapping and scheduling on the multiprocessor are discussed.
对系统的存储器结构、数据通信通道组成和系统总线结构进行了分析；讨论了算法划分、算法的多处理器映射及调度； - Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。 - To enhance the available cycle utilization efficiency of memory data bus, we propose a stream application oriented memory scheduling mechanism.
为了提高主存数据总线的有效周期利用率，提出了一种面向流应用的存储调度机制。 - This design uses two-port Random Access Memory ( RAM) in FPGA as data buffer, so it is very convenient because PCI-E bus and local bus can accesses it though respective port.
为了增加系统的灵活性，在FPGA中设计了双端口随机存储器（RAM）作为数据的缓存区，PCI-E总线和本地总线可以通过各自的接口对其独立的访问。